An insulated gate semiconductor device (i.e., IGBT) as a switching device for an inverter has been disclosed in, for example, JP 2007-13224A, US 2004/0094798 corresponding to JP 2004-95954A, U.S. Pat. No. 5,489,787 corresponding to JP 7-58332A, JP 2007-266134A, and JP 4366938.
Specifically, in JP 2007-13224A, trenches are formed in a high resistance N-type base layer at intervals to separate a main cell and a dummy cell form each other. The trench has a trench-gate structure. In the main cell, a P-type base layer is formed on the N-type base layer, and an N-type emitter layer is formed on the P-type base layer. Further, in the dummy cell, a P-type buffer layer is formed on the N-type base layer. The P-type base layer and the N-type emitter layer in the main cell are in contact with each other through an emitter electrode. A buffer electrode is formed on the P-type buffer layer in the dummy cell.
The buffer electrode is electrically connected to the emitter electrode through a buffer resistor. Thus, the P-type buffer layer in the dummy cell is emitter-grounded through the buffer resistor so that low switching loss can be achieved.
In US 2004/0094798, an N−-type epitaxial region is formed on an N+-type substrate, and a P-type base region is formed on the N−-type epitaxial region. A trench extending from a surface of the P-type base region to the N−-type epitaxial region is formed. A buried gate including a gate oxide layer and a gate electrode is formed in the trench. An interlayer dielectric layer is formed on the buried gate, and an N-type source region is formed around the trench.
Between the N−-type epitaxial region and the P-type base region, a thin P-type region and a thin N-type region are inserted on the bottom side of the trench over a cell region. Thus, depletion is substantially caused by PN junction between the P-type region and the N-type region. Accordingly, a parasitic capacitance is reduced so that low-on voltage can be achieved.
In U.S. Pat. No. 5,489,787, a P-type base layer is formed on an N−-type layer, and a trench extending form the P-type base layer to the N−-type layer is formed. A trench gate structure is formed in the trench. Further, an N+-type emitter region is formed around the trench gate structure on the surface side of the P-type base layer.
An N-type layer for storing carries between the N−-type layer and the P-type base layer is formed over a cell region. Since the N-type layer causes the carrier distribution in the N−-type layer to be close to the carrier distribution in a diode, low-on voltage can be achieved.
In JP 2007-266134A, two types of regions are formed on a surface of a semiconductor substrate. Specifically, in a first type region, a P-type first body region, an N+-type emitter region, and a P+-type first body region are formed. In a second type region, a P-type second body region, a P+-type second body region, and an N+-type accumulation region are formed. An N+-type emitter region is not formed in the second type region, and a P+-type second body contact region is formed to a surface portion of the second type region.
The accumulation region divides the second type region in two parts in its thickness direction. Further, the accumulation region extends to a position deeper than a bottom of the first body contact region of the first type region. Thus, since a parasitic transistor is not formed in the second type region where the accumulation region is formed, it is less likely that latch-up phenomenon occurs.
A structure disclosed in JP 4366938 is similar to the structure disclosed in JP 2007-266134A. In JP 4366938, trenches are formed in an N−-type drift layer to form semiconductor regions between the trenches. A gate insulating layer and a gate electrode are buried in the trench. The semiconductor regions include a first semiconductor region and a second semiconductor region. In the first semiconductor region, an N+-type emitter region is formed. In the second semiconductor region, an N+-type emitter region is not formed. The first region and the second region are alternately arranged. A P+-type emitter region deeper than the N+-type emitter region is formed in the first semiconductor region.
A P+-type emitter region is formed over a surface portion of the second semiconductor region, and an N+-type hole barrier region is formed below the P+-type emitter region. The N+-type hole barrier region is deeper than the P+-type emitter region of the first semiconductor region and is not in contact with the gate insulating layer. Thus, a path for holes flowing between the gate insulating layer and the N+-type hole barrier region is narrowed so that a reduction in holes in the drift region can be reduced. Accordingly, on-voltage of an IGBT can be reduced.
The above conventional devices have the following disadvantages.
Although JP 2007-13224A discloses a circuit diagram in which the buffer resistor is connected to the buffer electrode, it is practically difficult to uniformly arrange the buffer resistor over a semiconductor device having a trench gate structure as shown in the circuit diagram. This is because an actual buffer resistance can vary depending on location due to a wiring resistance.
In US 2004/0094798, the N-type region is located on the bottom side of the trench. In this case, if the N-type region is formed by thermal diffusion, the P-type base region as a channel needs to cancel the N-type region. Therefore, a threshold voltage (Vth) of the gate can have variations, and it is difficult to achieve high resistance to voltage breakdown. Further, if the N-type region is formed by ion implantation, a special apparatus for achieving high acceleration voltage is required to form the N-type region deep.
In U.S. Pat. No. 5,489,787, the N-type layer is formed on the P-type base layer and located near the N+-type emitter region. Therefore, a threshold voltage (Vth) of the gate can have variations, and resistance to voltage breakdown may be degraded due to thyristor action.
In JP 2007-266134A, the accumulation region formed in the second type region, where the N+-type emitter region is not formed, is deeper than the P+-type first body contact region.
In JP 4366938, the hole barrier region formed in the second semiconductor region, where the N+-type emitter region is not formed, is deeper than the P+-type emitter region.
A special equipment is required to form the hole accumulation region or the hole barrier region deeper than the first body contact region or the P+-emitter region. Further, it is difficult to accurately form the hole accumulation region or the hole barrier region at such a deep portion by ion implantation. FIG. 5A, which will be described later, shows a relationship between a projection range and an acceleration energy of ion implantation. FIG. 5B, which will be described later, shows a relationship between a projection range variation (dispersion) and the acceleration energy of ion implantation. As can be seen from FIGS. 5A and 5B, the projection range can be increased by increasing the acceleration energy. However, the increase in the acceleration energy results in an increase in the projection range variation. For example, although phosphorus (P) can be ion-implanted to a depth of 1.2 μm with an acceleration energy of 1000 keV, the projection range variation (one side) becomes about 0.2 μm, i.e., spreading in the depth direction becomes about 0.4 μm.
In the case of a reverse conducting IGBT (RC-IGBT), when a P+-type body region is formed, recover loss is increased due to an increase in the amount of holes injected during diode action. Specifically, to prevent undesirable parasitic transistor action from the point of view of resistance to surge, the P+-type body region has a high impurity concentration and is diffused deep so that P+-type body region can be located below an N-type emitter. Since the efficiency of hole injection in such a deep P+-type diffusion layer with a high impurity concentration is very high, the recover loss is increased.
As described above, the conventional devices have a difficulty in achieving both a low on-voltage and a low switching-loss.